1. Field of the Invention
This invention is related to the field of scan testing of integrated circuits, particularly dynamic logic circuits.
2. Description of the Related Art
Over time, larger numbers of transistors have been integrated into integrated circuits. As more transistors can be integrated, the functionality that can be realized in a given integrated circuit increases. The complexity of the integrated circuit similarly increases, and thus the ability to test the circuitry to ensure that it is functioning properly remains an important issue.
One mechanism used to test integrated circuits is scan testing (or, more briefly, “scan”). To support scan testing, various state elements (e.g. flops, latches, registers, etc.) are typically coupled together in a “scan chain”. The state elements may include separate scan-in inputs and/or scan-out outputs which may be connected together to form a scan chain. Alternatively, additional circuitry may mux the scan-in and functional inputs to the input of the state element and the output of the state element may be used for both scan values and functional values. Scan data is shifted into the scan chain, thus loading the state elements with a desired set of test data. The circuitry may be clocked functionally for one or more clock cycles, and then the result data may be shifted out of the scan chain. The result data may be compared to expected data to detect defects or improper operation.
In the past, dynamic circuitry has not been as fully tested as may be desired using scan. Dynamic circuitry is clocked, precharging and conditionally discharging based on a clock signal input. In some cases, for example, only the last stage in a dynamic circuit has been scannable, limiting the ability to use scan to test the dynamic circuits.